Because of the increase in the capacity of modern memories, the time spent on testing them increases correspondingly, which poses an extra cost for memory manufacturers. The ability to test a memory is important for ensuring normal operations of the memory as well as for saving costs.
The Built-in Self-Test (BIST) technology generally adopted by manufacturers is applied to testing if a memory is normal. In the architecture of the Memory Built-in Self-Test (MBIST), a built-in self-test circuit can be used to test the memory. The built-in self-test circuit provides a series of patterns, such as the march test or the checkboard pattern, to the memory. Then the circuit compares the outputs with an expected response. Because the patterns have high regularity, a comparator can be used to compare directly the outputs of the memory and the reference data to ensure that an error response coming from the memory is marked with a test fail.
US publication number 2004/0193984 and the U.S. Pat. No. 6,564,348 are examples of prior art approaches and architectures.
However, when the built-in self-test circuit according to the prior art tests a read-only memory (ROM), the compression technology is used for compressing a great deal of data stored in the ROM to a test signature, which is stored in a digital circuit of the chip beforehand. In mass production, testing is performed by comparing the signature of the memory to the compare signature stored in the digital circuit. Nevertheless, during the process of verification, when the data stored in the ROM needs to be modified, the chip must be re-laid-out to modify the pre-stored value, so that the compare signature stored in the digital circuit of the chip can be modified correspondingly. Consequently, the technology according to the prior art as described above needs to consume the limited hardware resources (needing extra digital circuitry of the chip for storing the compare signature in advance) and the time for engineering design (for example, engineering change of the chip).
Accordingly, it is desired to provide a novel memory with a self-test function and a method for testing the same, which can avoid consuming the limited hardware resources as well as reducing the engineering time and testing time.